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algorithm analysis applications architecture benchmark block buffer bytes calculation cell Cenju-4 cluster communication compiler directives constraints developed disk distributed dynamic Earth Simulator efficiency elements environment equations evaluate execution FIFO form factor Fortran function global graph grid hardware header hemisphere HP-PA IEEE implementation instruction interface iterative Java jitter L2 cache latency linear load balancing loop machine memory hierarchy mesh message passing method microprocessor multicast multiple multiprocessor multithreaded NASD neural network nodes number of processors OpenMP operations optimization overhead packet PAPIA parallel computer parallel processing parallel program parameters partitioning Pentium pipeline preconditioner prediction coverage problem Proc queue Radiosity ratio remote request resource runtime scheme sequential shared memory shows speedup static hybrid predictor storage structure submesh supernode superscalar switch synchronization Table task techniques Telegraphos thread tion value predictor variables vector vector processors workstations
Page iv - Graduate School of Information Science, Nara Institute of Science and Technology 8916-5 Takayama, Ikoma, Nara 630-0101, Japan...