Algorithms and Parallel VLSI Architectures II: Proceedings of the International Workshop, Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991Patrice Quinton, Yves Robert Since the emergence of VLSI, the relationship between the development of parallel algorithms and the design of special-purpose architecture has always been of major concern. The analysis of this relationship is the main topic of this book. Hardware and software issues closely depend upon one another and cannot be solved independently. Beyond the natural complexity of algorithm design, the designer has to face that of choosing the appropriate technology medium for its efficient realization. The dramatic developments in VLSI technology now offers extraordinary opportunities for implementing complex applications. As application specific/systems can offer 100 to 1000-fold improvements in cost/performance over general purpose computers on applications, they are attracting increasing attention in both academic and industrial communities. Highly specialized application-specific arrays of processors, which are the targeted architectures in this book, are extremely appealing. The papers in this volume give a thorough overview on current research in the areas of parallel algorithms, synthesis methods, VLSI architectures, and design tools. |
Contents
Orthogonal lattice algorithms for adaptive filtering | 11 |
Mapping QR decomposition of a banded matrix on a | 25 |
Algorithms and architectures for recursive total least | 39 |
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1992 Elsevier Science adder affine allocation application arithmetic B.V. All rights cells circuit clustering complexity computation constraints cycle defined delay denotes dependence vector derangement described digit domain dominating set edge efficient element Elsevier Science Publishers execution Figure filters function given graph hardware Hough transform hypercube IEEE implementation index set input integer interval graph iteration k-d tree Kung Lee and Kedem linear array linear filters mapping matrix multiplication memory MIMD nested loops node number of processors obtain on-line operator optimal output overskew parallel algorithms Parallel Computing PE's perform permutation pipelining pixels problem Proc processor array PSVA QR decomposition Quinton recurrence equations recursive regular array Robert eds SADC schedule Science Publishers B.V. Signal Processing SIMD simulation solution space space-time specification step structure switch synchronous synthesis systolic arrays techniques theorem transformation transputer true dependence shrinking tuple variable VLSI