Computer Architecture: A Quantitative Approach
The era of seemingly unlimited growth in processor performance is over: single chip architectures can no longer overcome the performance limitations imposed by the power they consume and the heat they generate. Today, Intel and other semiconductor firms are abandoning the single fast processor model in favor of multi-core microprocessors--chips that combine two or more processors in a single package. In the fourth edition of Computer Architecture, the authors focus on this historic shift, increasing their coverage of multiprocessors and exploring the most effective ways of achieving parallelism as the key to unlocking the power of multiple processor architectures. Additionally, the new edition has expanded and updated coverage of design topics beyond processor performance, including power, reliability, availability, and dependability.
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Increased coverage on achieving parallelism with multiprocessors.
Case studies of latest technology from industry including the Sun Niagara Multiprocessor, AMD Opteron, and Pentium 4.
Three review appendices, included in the printed volume, review the basic and intermediate principles the main text relies upon.
Eight reference appendices, collected on the CD, cover a range of topics including specific architectures, embedded systems, application specific processors--some guest authored by subject experts.
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InstructionLevel Parallelism and Its Exploitation
Limits on InstructionLevel Parallelism
Multiprocessors and ThreadLevel Parallelism
Memory Hierarchy Design
Basic and Intermediate Concepts
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ADD.D addressing modes Appendix architecture assume average memory access bandwidth benchmarks bits branch prediction buffer bytes cache block cache misses Chapter chip clock cycles clock rate coherence compiler complete cost data cache dependences disk DRAM dynamic scheduling entry example execution fetch Figure floating-point functional units hardware hazards implementation increase instruction set instruction set architecture instruction-level parallelism integer Intel invalidate issue L2 cache latency load loop main memory memory hierarchy microprocessors MIPS misprediction miss penalty miss rate MTTF multiple multiprocessor node operands operating system Opteron optimizations Pentium performance physical address pipeline predictor prefetch processor programs protocol queue RAID register renaming renaming requests requires reservation stations result RISC server set associative shared shows snooping speculation speedup superscalar thread-level parallelism tion virtual address virtual memory workload
Page R-8 - A new theory of deadlock-free adaptive routing in wormhole networks," IEEE Trans, on Parallel and Distributed Systems, vol. 4, no. 12, pp.